Field of the Invention
The invention lies in the field of semiconductor technology. More specifically, the invention pertains to a method of testing an integrated circuit equipped with a memory and a test circuit.
In addition to logic circuits, use is increasingly being made of so-called embedded memory cores in integrated circuits. Such memories are used to store data that arise from inside the integrated circuit or are required by the latter. It is thereby not necessary for the functioning of the integrated circuit to access the memory from outside the integrated circuit. Testing of the operability of the memory is necessary, nevertheless. An extensive test requires both that the addresses and data patterns be generated algorithmically and applied to terminals of the memory, and that the time response of the applied addresses, the data to be stored, and the control signals be changed.
In order to carry out a test of a memory core, it can be provided to connect all the terminals of the memory to external terminals of the integrated circuit, at least while it is being tested (so-called release). However, this requires a large number of external terminals and the presence of a memory tester for connection to the external terminals, which generates the required algorithmic test patterns.
A further possibility for carrying out the functional testing of the memory is the so-called Built-In Self Test (BIST). Testing the memory is undertaken by a test circuit, which is provided on the integrated circuit, generates the test patterns and also fixes the timing of the corresponding signals. It is impossible in this case to influence the testing from outside the integrated circuit. After the self test has been carried out completely, all that is then required is to transmit a single result signal (Go-/No-Go signal) to outside the integrated circuit, for which purpose a single test signal output suffices in the extreme case. By contrast with the first mentioned solution, this one does have the advantage of avoiding a large number of test pins and of managing without an external test device with a large number of test terminals. However, a BIST has the disadvantage that thorough testing requires a large number of different test patterns and time responses to be generated by the test circuit located on the integrated circuit.
A large outlay is required in order to be able to undertake a variation in the timing in the case of a BIST. This requires, inter alia, timing generators in the corresponding test circuit (for example in the form of ring counters) and comparators. This additional outlay on circuitry weighs very heavily particularly in the case of memories to be tested which have a low storage capacity.
A memory which is connected to an internal test circuit via a circuit configuration is described in European patent application EP 0 213 037 A. The circuit configuration is controlled from outside and connects the memory to the test circuit in a test mode, while it connects the memory to external terminals in a normal mode.
An integrated circuit having a memory and a test device is specified in European patent application EP 0 053 665 A. The test device feeds data and addresses to the memory via gates controlled from outside the integrated circuit. Control signals are fed directly to the memory from outside the integrated circuit.